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ds05-11142-1e fujitsu semiconductor data sheet memory un-buffered 4 m 64 bit synchronous dynamic ram dimm mb8504s064ca-102/-103/-102l/-103l 168-pin, 4 clock, 1-bank, based on 4 m 16 bit sdrams with spd n description the fujitsu mb8504s064ca is a fully decoded, cmos synchronous dynamic random access memory (sdram) module consisting of four mb81f641642c devices which organized as four banks of 4 m 16 bits and a 2k-bit serial eeprom on a 168-pin glass-epoxy substrate. the mb8504s064ca features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the mb8504s064ca is optimized for those applications requiring high speed, high performance and large memory storage, and high density memory organizations. this module is ideally suited for workstations, pcs, laser printers, and other applications where a simple interface is needed. n product line & features parameter mb8504s064ca-102/-102l mb8504s064ca-103/-103l cl-t rcd -t rp 2-2-2 clk min. 3-2-2 clk min. clock frequency 100 mhz max. 100 mhz max. burst mode cycle time 10 ns min. 10 ns min. output valid from clock 6 ns max. (cl = 2) 6 ns max. (cl = 3) power dissipation two banks active 2736 mw max. 2736 mw max. self refresh mode 14.4 mw max. (std. power) 7.2 mw max. (low power) 14.4 mw max. (std. power) 7.2 mw max. (low power) ? un-buffered 168-pin dimm socket type (lead pitch: 1.27 mm) ? conformed to jedec standard (4 clk) ? organization: 4,194,304 words 64 bits ? memory: mb81f641642c (4 m 16, 4-bank) 4 pcs ? 3.3 v 0.3 v supply voltage ? all input/output lvttl compatible ? conformed to intel pc/100 spec. ? 4096 refresh cycle every 65.6 ms ? auto and self refresh ? cke power down mode ? dqm byte masking (read/write) ? serial presence detect (spd) with serial eeprom: intel spd spec rev 1.2a format ? module size: 1.375 (height) 5.25 (length) 0.157 (thickness) to top / lineup / index
2 mb8504s064ca-102/-103/-102l/-103l n pac k ag e package and ordering information C 168-pin dimm, order as mb8504s064ca- dg (dg = std. power ver., gold pad) mb8504s064ca- ldg (ldg = low power ver., gold pad) 168-pin plastic dimm (socket type) (mds-168p-p40) to top / lineup / index
3 mb8504s064ca-102/-103/-102l/-103l n pin assignments pin no. signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1v ss 29 dqmb 1 57 dq 18 85 v ss 113 dqmb 5 141 dq 50 2dq 0 30 cs 0 58 dq 19 86 dq 32 114 n.c. 142 dq 51 3dq 1 31 n.c. 59 v cc 87 dq 33 115 ras 143 v cc 4dq 2 32 v ss 60 dq 20 88 dq 34 116 v ss 144 dq 52 5dq 3 33 a 0 61 n.c. 89 dq 35 117 a 1 145 n.c. 6v cc 34 a 2 62 n.c. 90 v cc 118 a 3 146 n.c. 7dq 4 35 a 4 63 n.c. 91 dq 36 119 a 5 147 n.c. 8dq 5 36 a 6 64 v ss 92 dq 37 120 a 7 148 v ss 9dq 6 37 a 8 65 dq 21 93 dq 38 121 a 9 149 dq 53 10 dq 7 38 a 10 66 dq 22 94 dq 39 122 ba 0 150 dq 54 11 dq 8 39 ba 1 67 dq 23 95 dq 40 123 a 11 151 dq 55 12 v ss 40 v cc 68 v ss 96 v ss 124 v cc 152 v ss 13 dq 9 41 v cc 69 dq 24 97 dq 41 125 clk 1 153 dq 56 14 dq 10 42 clk 0 70 dq 25 98 dq 42 126 n.c. 154 dq 57 15 dq 11 43 v ss 71 dq 26 99 dq 43 127 v ss 155 dq 58 16 dq 12 44 n.c. 72 dq 27 100 dq 44 128 cke 0 156 dq 59 17 dq 13 45 cs 2 73 v cc 101 dq 45 129 n.c. 157 v cc 18 v cc 46 dqmb 2 74 dq 28 102 v cc 130 dqmb 6 158 dq 60 19 dq 14 47 dqmb 3 75 dq 29 103 dq 46 131 dqmb 7 159 dq 61 20 dq 15 48 n.c. 76 dq 30 104 dq 47 132 n.c. 160 dq 62 21 n.c. 49 v cc 77 dq 31 105 n.c. 133 v cc 161 dq 63 22 n.c. 50 n.c. 78 v ss 106 n.c. 134 n.c. 162 v ss 23 v ss 51 n.c. 79 clk 2 107 v ss 135 n.c. 163 clk 3 24 n.c. 52 n.c. 80 n.c. 108 n.c. 136 n.c. 164 n.c. 25 n.c. 53 n.c. 81 n.c. (wp) 109 n.c. 137 n.c. 165 sa 0 26 v cc 54 v ss 82 sda 110 v cc 138 v ss 166 sa 1 27 we 55 dq 16 83 scl 111 cas 139 dq 48 167 sa 2 28 dqmb 0 56 dq 17 84 v cc 112 dqmb 4 140 dq 49 168 v cc to top / lineup / index
4 mb8504s064ca-102/-103/-102l/-103l n pin descriptions symbol i/o function symbol i/o function a 0 to a 11 i address input dq 0 to dq 63 i/o data input/data output ba 0 , ba 1 i bank select (bank address) v cc power supply (+3.3 v) ras i row address strobe v ss ground (0 v) cas i column address strobe n.c. no connection we i write enable sa 0 to sa 2 i serial pd address input dqmb 0 to dqmb 7 i data (dq) mask scl i serial pd clock clk 0 to clk 3 i clock input sda i/o serial pd address/data input/output cke 0 i clock enable wp serial pd write protect cs 0 , cs 2 i chip select top view d 0 1 84 plane 0 85 168 plane 1 34.93 mm 133.37 mm (mds-168p-p40) d 1 d 3 d 4 10 94 11 95 40 124 41 125 to top / lineup / index
5 mb8504s064ca-102/-103/-102l/-103l n serial-pd information note: any write operation must not be executed into the addresses of byte 0 to byte 127. some or all data stored into byte 0 to byte 127 may be broken. *1. byte 22: sdram device attributes *2. byte 63: checksum for byte 0 to 62 this byte is the checksum for byte 0 through 62. this byte contains the value of the low 8-bits of the arithmetic sum of byte 0 through 62. byte function described hex value -102/ 102l -103/ 103l 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 to 61 62 63 64 to 71 72 73 to 90 91 to 92 93 to 94 95 to 98 99 to 125 126 127 128+ defines number of bytes written into serial memory at module manufacture total number of bytes of spd memory device fundamental memory type number of row addresses number of column addresses number of module banks data width data width (continuation) interface type sdram cycle time (highest cas latency) sdram access from clock (highest cas latency) dimm configuration type refresh rate/type primary sdram width error checking sdram width minimum clock delay for back to back random column addresses burst lengths supported number of banks on each sdram device cas latency supported cs latency write latency sdram module attributes sdram device attributes : general sdram cycle time (2nd. highest cas latency) sdram access from clock (2nd. highest cas latency) sdram cycle time (3rd. highest cas latency) sdram access from clock (3rd. highest cas latency) minimum row precharge time (t rp ) row activate to row activate minimum (t rrd ) ras to cas delay min. (t rcd ) minimum ras pulse width module bank density command and address signal input setup time command and address signal input hold time data signal input setup time data signal input hold time unused storage locations spd data revision code checksum for byte 0 to 62 manufacturers jedec id code per jep-108e manufacturing location manufacturers part number revision code manufacturing data assembly serial number manufacturer specific data intel specification frequency intel specification details for 100 mhz support unused storage locations 128 byte 256 byte sdram 12 8 1 bank 64 bit +0 lvttl 10/10 ns 6/6 ns non-parity self, normal 16 0 1 cycle 1, 2, 4, 8, page 4 bank 2, 3 0 0 un-buffer *1 10/15 ns 6/8 ns no support no support 20/20 ns 20/20 ns 20/20 ns 50/50 ns 32 mbyte 2 ns 1 ns 2 ns 1 ns 1.2 *2 optional optional optional optional optional optional optional 100 mhz cl = 2, 3 / 3 80h 08h 04h 0ch 08h 01h 40h 00h 01h a0h 60h 00h 80h 10h 00h 01h 8fh 04h 06h 01h 01h 00h 0eh a0h 60h 00h 00h 14h 14h 14h 32h 08h 20h 10h 20h 10h 00h 12h 04h 00h 00h 00h 00h 00h 00h 00h 64h afh 80h 08h 04h 0ch 08h 01h 40h 00h 01h a0h 60h 00h 80h 10h 00h 01h 8fh 04h 06h 01h 01h 00h 0eh f0h 80h 00h 00h 14h 14h 14h 32h 08h 20h 10h 20h 10h 00h 12h 74h 00h 00h 00h 00h 00h 00h 00h 64h adh bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tbd tbd upper v cc tolerance lower v cc tolerance supports write 1 /read burst supports precharge all supports auto- precharge supports early ras precharge 00001110 to top / lineup / index
6 mb8504s064ca-102/-103/-102l/-103l block diagram v cc clk 3 serial pd clk 0 10 w clk 1 clk: sdram d0,1 + 15 pf sda clk 2 10 w clk: sdram d3, 4 + 15 pf n.c. (wp) v ss scl sa 2 sa 1 sa 0 ras cas we a (11:0) ba 0 ras : sdramd0-1, 3-4 cas : sdram d0-1, 3-4 we : sdram d0-1, 3-4 a (11:0): sdram d0-1, 3-4 a 13 : sdram d0-1, 3-4 10 w 10 w 10 w 10 w cs 0 dqmb 0 dq (7:0) dqmb 4 dqmb 2 dqmb 6 dq (39:32) dq (23:16) dq (55:48) 4m 16 d0 v ss v cc : sdram v ss : sdram 10 w 10 w 47 k w ba 1 a 12 : sdram d0-1, 3-4 c cke 0 cke: sdram d0-1, 3-4 v ss c v ss c 4m 16 d3 cs 2 10 w 10 w dqmb 1 dq (15:8) dqmb 5 dq (47:40) 4m 16 d1 10 w 10 w dqmb 3 dq (31:24) dqmb 7 dq (63:56) 4m 16 d4 to top / lineup / index
7 mb8504s064ca-102/-103/-102l/-103l n absolute maximum ratings (see warning) * : voltages referenced to v ss (= 0 v) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions *1. voltages referenced to v ss (=0v) *2. overshoot limit: v ih (max.) = v cc +1.5 v with a pulse-width 5 ns. *3. undershoot limit: v il (min.) = C1.5 v with a pulse-width 5 ns. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating conditionranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit min. max. supply voltage* v cc C0.5 +4.6 v input voltage* v in C0.5 +4.6 v output voltage* v out C0.5 +4.6 v storage temperature t stg C55 +125 c power dissipation p d 4.0w output current (d.c.) i out C50 +50 ma parameter notes symbol value unit min. typ. max. supply voltage *1 v cc 3.0 3.3 3.6 v v ss 000v input high voltage, all inputs *1, 2 v ih 2.0 v cc +0.5 v input low voltage, all inputs *1, 3 v il C0.5 0.8 v ambient temperature t a 0+70 c to top / lineup / index
8 mb8504s064ca-102/-103/-102l/-103l n capacitance (v cc = +3.3 v, f = 1 mhz, t a = +25 c) parameter symbol value unit min. max. input capacitance a 0 to a 11 , ba 0 , ba 1 c in1 t.b.d. pf ras , cas , we c in2 t.b.d. pf cs 0 , cs 2 c in3 t.b.d. pf cke 0 c in4 t.b.d. pf clk 0 to clk 3 c in5 t.b.d. pf dqmb 0 to dqmb 7 c in6 t.b.d. pf scl c scl t.b.d. pf sa 0 , sa 1 , sa 2 c sa t.b.d. pf input/output capacitance sda c sda t.b.d. pf dq 0 to dq 63 c dq t.b.d. pf to top / lineup / index
9 mb8504s064ca-102/-103/-102l/-103l n dc characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2 (continued) parameter notes symbol condition value unit min. max. std. ver. low ver. operating current (average power supply current) *3 i cc1s burst length = 4, t rc = min for bl = 4, t ck = min, one bank active, outputs open, address changed up to 3 times during t rc (min.), 0 v v in v cc 420ma i cc1d burst length = 4 (each bank), t rc = min for bl = 4 (each bank), t ck = min, two banks active, outputs open, address changed up to 3 times during t rc (min.), 0 v v in v cc 760ma precharge standby current (power supply current) *3 i cc2p cke = v il , t ck = min, all banks idle, power down mode, 0 v v in v cc 8 4ma i cc2ps cke = v il , clk = v ih or v il , all banks idle, power down mode, 0 v v in v cc 4 2ma i cc2n cke = v ih , t ck = min, all banks idle, nop commands only, input signals (except to cmd) are changed one time during 3 clock cycles, 0 v v in v cc 60ma i cc2ns cke = v ih , clk = v ih or v il , all banks idle, input signals are stable, 0 v v in v cc 8ma to top / lineup / index
10 mb8504s064ca-102/-103/-102l/-103l (continued) notes: *1. an initial pause (desl on nop) of 200 m s is required after power-on followed by a minimum of eight auto-refresh cycles. *2. dc characteristics is the serial pd standby state (v in = gnd or v cc ). *3. i cc depends on the output termination, load conditions, clock cycle rate and signal clock rate. the specified values are obtained with the output open and no termination resistors. *4. voltages referenced to v ss (= 0 v) parameter notes symbol condition value unit min. max. std. ver. low ver. active standby current (power supply current) *3 i cc3p cke = v il , t ck = min, any bank active, 0 v v in v cc 8 4ma i cc3ps cke = v il , clk = v ih or v il , any bank active, 0 v v in v cc 4 2ma i cc3n cke = v ih , t ck = min, any bank active, nop commands only, input signals (except to cmd) are changed one time during 3 clock cycles, 0 v v in v cc 100ma i cc3ns cke = v ih , clk = v ih or v il , any bank active, 0 v v in v cc 8ma burst mode current (average power supply current) *3 i cc4 t ck = min, gapless data, burst length = 4, outputs open, multiple-banks active, 0 v v in v cc 340ma auto-refresh current (average power supply current) *3 i cc5 auto refresh, t ck = min, t rc = min, 0 v v in v cc 960ma self-refresh current (average power supply current) *3 i cc6 self-refresh, t ck = min, cke 0.2 v , 0 v v in v cc 4 2ma input leakage current (all inputs) i li 0 v v in v cc all other pins not under test = 0 v C40 40 m a output leakage current i lo output is disabled (hi-z) 0 v v in v cc C10 10 m a lvttl output high voltage *4 v oh i oh = C2.0 ma 2.4 v lvttl output low voltage *4 v ol i ol = +2.0 ma 0.4 v to top / lineup / index
11 mb8504s064ca-102/-103/-102l/-103l n ac characteristics (sdram component specifications) notes 1, 2, 3 (1) base characteristics (at recommended operating conditions unless otherwise noted.) no. parameter notes symbol mb8504s064ca -102/-102l mb8504s064ca -103/-103l unit min. max. min. max. 1clock period cl = 2 t ck2 10 15 ns cl = 3 t ck3 10 10 2 clock high time t ch 33ns 3clock low time t cl 33ns 4 input setup time t si 22ns 5 input hold time t hi 11ns 6 output valid from clock (t clk = min) *4, *5 cl = 2 t ac2 68 ns cl = 3 t ac3 66 7 output in low-z t lz 00ns 8 output in high-z *6 cl = 2 t hz2 3638 ns cl = 3 t hz3 3636 9 output hold time t oh 33ns 10 time between refresh t ref 65.6 65.6 ms 11 transition time t t 0.520.52ns 12 cke setup time for power down exit time t cksp 33ns to top / lineup / index
12 mb8504s064ca-102/-103/-102l/-103l (2) base values for clock count/latency (3) clock count formula (*9) (4) latency (the latency values on these parameters are fixed regardless of clock period.) no. parameter notes symbol mb8504s064ca -102/-102l mb8504s064ca -103/-103l unit min. max. min. max. 1ras cycle time *7 t rc 70 70 ns 2ras precharge time t rp 20 20 ns 3ras active time t ras 50 110000 50 110000 ns 4ras to cas delay time *8 t rcd 20 20 ns 5 write recovery time t wr 10 10 ns 6 data-in to precharge lead time t dpl 10 10 ns 7 data-in to active/refresh command period cl = 2 t dal2 1 cyc + t rp 1 cyc + t rp ns cl = 3 t dal3 2 cyc + t rp 2 cyc + t rp 8 mode register set cycle time t rsc 20 20 ns 9 ras to ras bank active delay time t rrd 20 20 ns no. parameter symbol mb8504s064ca -102/-102l mb8504s064ca -103/-103l unit 1 cke to clock disable i cke 11cycle 2 dqm to output in high-z i dqz 22cycle 3 dqm to input data delay i dqd 00cycle 4 last output to write command delay i owd 22cycle 5 write command to input data delay i dwd 00cycle 6 precharge to output in high-z delay cl = 2 i roh2 22 cycle cl = 3 i roh3 33 7 burst stop command to output in high-z delay cl = 2 i bsh2 22 cycle cl = 3 i bsh3 33 8cas to cas delay (min) i ccd 11cycle 9cas bank delay (min) i cbd 11cycle clock 3 base value clock period (round off a whole number) to top / lineup / index
13 mb8504s064ca-102/-103/-102l/-103l notes: *1. an initial pause (desl on nop) of 200 m s is required after power-up followed by a minimum of eight auto-refresh cycles. *2. 1.4 v or v ref is the reference level for measuring timing of signals. transition times are measured between v ih (min) and v il (max). *3. ac characteristics assume t t = 1 ns and 50 pf of capacitance load. *4. assumes t rcd is satisfied. *5. t ac also specifies the access time at burst mode except for first access. *6. specified where output buffer is no longer driven. *7. actual clock count of t rc (i rc ) will be sum of clock count of t ras (i ras ) and t rp (i rp ). *8. operation within the t rcd (min) ensures that access time is determined by t rcd (min) +t ac (max) ; if t rcd is greater than the specified t rcd (min), access time is determined by t ac . *9. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *source: see mb81f641642c data sheet for details on the electrical. n ac operating test condition (example of ac test load circuit) i/o z = 50 w 50 w 1.4 v 50 pf to top / lineup / index
14 mb8504s064ca-102/-103/-102l/-103l n serial presence detect(spd) function 1. pin descriptions scl (serial clock) scl input is used to clock all data input/output of spd. sda (serial data) sda is a common pin used for all data input/output of spd. the sda pull-up resistor is required due to the open-drain output. sa 0 , sa 1 , sa 2 (address) address inputs are used to set the least significant three bits of the eight bits slave address. the address inputs must be fixed to select a particular module and the fixed address of each module must be different each other. 2. spd operations clock and data convention data states on the sda can change only during sc l= low. sda state changes during scl = high are indicated start and stop conditions. refer to fig. 1 below. start condition all commands are preceded by a start condition, which is a transition of sda state from high to low when scl = high. spd will not respond to any command until this condition has been met. stop condition all read or write operation must be terminated by a stop condition, which is a transition of sda state from low to high when scl = high. the stop condition is also used to make the spd into the state of standby power mode after a read sequence. start fig. 1 C start and stop conditions stop scl sda start = high to low transition of sda state when scl is high stop = low to high transition of sda state when scl is high to top / lineup / index
15 mb8504s064ca-102/-103/-102l/-103l acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will put the sda line to low in order to acknowledge that it received the eight bits of data. the spd will respond with an acknowledge when it received the start condition followed by slave address issued by master. in the read operation, the spd will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is issued by master, the spd will continue to transmit data. if an acknowledge is not detected, the spd will terminated further data transmissions. the master must then issue a stop condition to return the spd to the standby power mode. in the write operation, upon receipt of eight bits of data the spd will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master. slave address addressing following a start condition, the master must output the eight bits slave address. the most significant four bits of the slave address are device type identifier. for the spd this is fixed as 1010[b]. refer to the fig. 2 below. the next three significant bits are used to select a particular device. a system could have up to eight spd devices namely up to eight modules on the bus. the eight addresses for eight spd devices are defined by the state of the sa 0 , sa 1 and sa 2 inputs. the last bit of the slave address defines the operation to be performed. when r/w bit is 1, a read operation is selected, when r/w bit is 0, a write operation is selected. following the start condition, the spd monitors the sda line comparing the slave address being transmitted with its slave address (device type and state of sa 0 , sa 1 , and sa 2 inputs). upon a correct compare the spd outputs an acknowledge on the sda line. depending on the state of the r/w bit, the spd will execute a read or write operation. 1 0 1 0 r/w sa 2 sa 1 sa 0 device type identifier device address fig. 2 C slave address to top / lineup / index
16 mb8504s064ca-102/-103/-102l/-103l 3. read operations current address read internally the spd contains an address counter that maintains the address of the last data accessed, incremented by one. therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). upon receipt of the slave address with the r/w bit = 1, the spd issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig. 3 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit = 1, the master must first perform a dummy write operation on the spd. the master issues the start condition, and the slave address followed by the word address. after the word address acknowledge, the master immediately reissues the start condition and the slave address with the r/ w bit = 1. this will be followed by an acknowledge from the spd and then by the eight bits of data. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig. 4 for the sequence of address, acknowledge and data transfer. fig. 3 C current address read s t o p data a c k slave address s t a r t bus activity : master sda line bus activity : spd fig. 4 C random read s t o p data a c k slave address a c k a c k slave address word address s t a r t s t a r t bus activity : master sda line bus activity : spd to top / lineup / index
17 mb8504s064ca-102/-103/-102l/-103l sequential read sequential read can be initiated as either a current address read or random read. the first data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. the spd continues to output data for each acknowledge received. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig. 5 for the sequence of address, acknowledge and data transfer. the data output is sequential, with the data from address(n) followed by the data from address(n+1). the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space (address 255), the counter rolls over to address 0 and the spd continues to output data for each acknowledge received . 4. dc characteristics note: *1. referenced to v ss . parameter note symbol condition value unit min. max. input leakage current s ili 0 v v in v cc C10 10 m a output leakage current s ilo 0 v v out v cc C10 10 m a output low voltage *1 s vol i ol = 3.0 ma 0.4 v fig. 5 C sequential read s t o p a c k a c k a c k data (n+x) data (n+2) data (n+1) data (n) slave address a c k bus activity : master sda line bus activity : spd to top / lineup / index
18 mb8504s064ca-102/-103/-102l/-103l 5. ac characteristics no. parameter symbol value unit min. max. 1 scl clock frequency f scl 100 khz 2 noise suppression time constant at scl, sda inputs t i 100 ns 3 scl low to sda data out valid t aa 3.5 m s 4 time the bus must be free before a new transmission can start t buf 4.7 m s 5 start condition hold time t hd:sta 4.0 m s 6clock low period t low 4.7 m s 7 clock high period t high 4.0 m s 8 start condition setup time t su:sta 4.7 m s 9 data in hold time t hd:dat 0 m s 10 data in setup time t su:dat 250 ns 11 sda and scl rise time t r 1 m s 12 sda and scl fall time t f 300 ns 13 stop condition setup time t su:sto 4.7 m s 14 data out hold time t dh 100 ns 15 write cycle time t wr 15ms t f t high t low t r t hd : dat t su : dat t su : sto t aa t dh t buf t hd : sta scl sda (input) sda (output) t su : sta fig. 6 C timing waveform to top / lineup / index
19 mb8504s064ca-102/-103/-102l/-103l n package dimension c 1998 fujitsu limited m168040sc-1-1 84 1 65.68?.13(2.586?005) 66.68?.13(2.625?005) c l 131.35?.13(5.171?005) 133.35?.13(5.250?005) 4.00?.10 (.157?004) 2-3.00?.05 (2-.118?002) 3.00?.13 (.118?005) 34.925?.13 (1.375?005) 3.17?.13 (.125?005) 36.83?.05 (1.450?002) 11.43?.05 (.450?002) c l 1.27?.03 (.050?001) 54.61?.05(2.150?002) 115.57?.13(4.550?005) 127.35?.13(5.014?005) pin no.1 index. .050 ?003 +.004 ?.08 +0.10 1.27 17.78?.13 (.700?005) "a" "b" "c" 1.00?.05 (.039?002) details of "c" part c l 2.54(.100)typ. 0.25(.010)max. details of "b" part 4.00(.157)min. 2.00?.10(.079?004) 1.00?.05(.039?002) 6.35?.13 (.250?005) 2.00?.10(.079?004) 1.00?.05(.039?002) details of "a" part 3.81(.150)max. 3.00(.118)min. 6.35?.13 (.250?005) (1.661?005) 42.18?.13 128.93?.13(5.076?005) 4-r1.27?.10 (4-r.05?004) 22.25?.13 (.876?005) 9.53?.10 notches full r (.375?004) .118 ? +.010 ? +0.25 3.00 3.00 +0.25 ? +.010 ? .118 dimension in mm (inches) 168-pin plastic dimm (socket type) (mds-168p-p40) to top / lineup / index
20 mb8504s064ca-102/-103/-102l/-103l fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9901 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. to top / lineup / index

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